doi: 10.7763/IJCTE.2011.V3.320
Design and Implementation of High Speed II Rand FIR Filter using Pipelining
- 1DAV Institute of Engineering & Technology, Jalandhar, India.
- 2Institute of Technology, Jalandhar, India
Abstract
The FIR & IIR Filters are being designed using HDL languages since speed is among the chief interest in this era; the main objective is to enhance the speed of the system. In the whole system if the speed of the individual block is enhanced the overall speed of the system is enhanced digital computer arithmetic is an aspect of logic design with the objective of developing appropriate algorithms in order to attain an effective utilization of the available hardware. Since ultimately, speed, power and chip area are the most of ten used measures ofthe efficiency of an algorithm, there has a strong link between the algorithms and technology applied for its implementation. Here it is done by applying the technique pipelining. The comparative analysis of pipelined & non-pipelined FIR and IIR filters is performed by using different FPGA’s. The result sreveal that the implemented filters turn in a consistent quality of output.
Keywords
- Infinite impulse response (IIR)
- Finite impulse response (FIR)
- Pipelining
- Field programmable gate arrays
How to Cite
Ravinder Kaur, Ashish Raman, Hardev Singh, and Jagjit Malhotra, "Design and Implementation of High Speed II Rand FIR Filter using Pipelining," International Journal of Computer Theory and Engineering, vol. 3, no. 2, pp. 292-295, 2011. https://doi.org/10.7763/IJCTE.2011.V3.320
Copyright & License
Copyright © 2011 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).