International Journal of Computer Theory and Engineering

Editor-In-Chief: Prof. Mehmet Sahinoglu
Frequency: Quarterly
ISSN: 1793-8201 (Print), 2972-4511 (Online)
Publisher:IACSIT Press

OPEN ACCESS
4.0
CiteScore

IJIET 2010 Vol.2(3): 333-337
doi: 10.7763/IJCTE.2010.V2.163

Realization of BCD adder using Reversible Logic

X. Susan Christina , M. Sangeetha Justine , K. Rekha , U. Subha , R. Sumathi

  • department of Electronics and Communication Engineering Mookambigai College of Engineering, Pudukottai-60, India. fab_jesu@yahoo.co.in

Abstract

This paper proposes novel carry select and carry look-ahead BCD adders using reversible logic. Reversible logic gates are widely known to be compatible with future computing technologies which virtually dissipate zero heat. Adders are fundamental building blocks in many computational units. For this reason, we have simulated several adder circuits using the reversible gates. Among all the other adders, the main virtue of BCD adders is that it allows easy conversion to decimal digits for printing or display and faster decimal calculations. These reversible BCD circuits are basis of the decimal ALU of primitive Quantum CPU. The proposed BCD adders have been simulated in VLSI and static timing report was analyzed.

Keywords

  • Reversible logic gates
  • BCD adder
  • quantum computing
163-G578

How to Cite

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X. Susan Christina, M. Sangeetha Justine, K. Rekha, U. Subha, and R. Sumathi, "Realization of BCD adder using Reversible Logic," International Journal of Computer Theory and Engineering, vol. 2, no. 3, pp. 333-337, 2010. https://doi.org/10.7763/IJCTE.2010.V2.163

Copyright & License

Copyright © 2010 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).

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