Abstract—A five stage pipelined architecture is proposed to target real-time video resolution conversion in spatial domain. This low complexity design is based on pre-computed memory mapping which computes the geometric position of interpolated pixels and their gray level values based on the scaling factor. The memory map has been conceived using nearest neighbor interpolation technique which simplifies the implementation. The scaling ratio is provided as an input to the hardware architecture before conversion. The design is capable of converting any video frame size in real-time. The memory requirement in this operation has been significantly reduced in comparison with earlier hardware based schemes. The results have been validated on a Xilinx Spartan FPGA running at 100 MHz Conversion times for different scaling ratios have been reported.
Asmar A. Khan, School of Computing and Communications, Lancaster University, LA1 4WA, UK (Email: a.khan3@lancaster.ac.uk)
Cite: Asmar A. Khan, "Low Complexity Pipelined Architecture for Real-Time Generic Video Scaling," International Journal of Computer Theory and Engineering vol. 3, no. 4, pp. 557-560, 2011.
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