International Journal of Computer Theory and Engineering

Abstract

In this paper we presents the design of low power i.e 0.69mW and 700MHz, 8 x 8-bit digital multiplier providing a better performance and lower power dissipation than the conventional linear array multipliers in two folds of speed and power consumption. The modified pair-wise and parallel addition algorithms [2] provide high speed multiplication and lower power dissipation in this work. The power performance of individual block is pre evaluated to identify the most power consuming element and attempt is to select the most efficient topology to reduce the power consumption of entire multiplier while maintaining the high operating frequency. The proposed multiplier has been designed and implemented employing Tanner 0.18 μm CMOS technology and analyzed using TSPICE. When the multiplier is targeted to a maximum operating frequency of 700 MHz at VDD equal to 1.8 V, it dissipates 0.69 mW. For comparison purposes a Baugh-Wooley multiplier is redesigned and optimized. The simulation results are compared showing superiority of proposed multiplier in both power and speed performance.