doi: 10.7763/IJCTE.2012.V4.432
A P System Simulator for Logic Gates
Amged Fathey
, ,
- Computer Science Department, Faculty of Computers Science, MTI University, Cairo, Egypt.
Abstract
The objectives of this paper are representing a simulator for the logic gates using P systems with priorities rules, and making use of the P system parallel computing in order to reduce the time used to test or evaluate a logic circuit (set of logic gates), which may change the vision of the current logic gates systems. Also, introducing the basic logic gates and how they work together, the development of the appropriate P system models for these gates are represented, and putting all together in order to get logic circuits which are P system based, finally a simulation and a test for them using a P Lingua language simulator, and an example is introduced to illustrate and making test of the model.
Keywords
- Logic gates
- membrane computing
- p-lingua
- p system
- simulator
How to Cite
Amged Fathey, Amr Badr, and Ibrahim Farag, "A P System Simulator for Logic Gates," International Journal of Computer Theory and Engineering, vol. 4, no. 1, pp. 98-102, 2012. https://doi.org/10.7763/IJCTE.2012.V4.432
Copyright & License
Copyright © 2012 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).