doi: 10.7763/IJCTE.2012.V4.584
Improvement of Optimization in Design of Synchronous Sequential Circuits by Using Evolvable Hardware
P. Soleimani1
,
S. Mirzakuchaki2 ,
R. Sabbaghi-Nadooshan1 ,
M. Bagheri2
- 1Department of electronic engineering, Islamic Azad University, Central Tehran Branch.
- 2Department of electronic engineering, Iran University, of Science and Technology.
Abstract
Evolvable hardware is a new method for designing the digital logic circuits. In this paper, a method has been presented for designing the synchronous sequential logic circuit by using the evolvable hardware. In this approach, the sequential logic circuit is divided into two sections; the combinational logic circuit and DFFs. The combinational logic part is designed by using a constant structure and their connections are set with genetic algorithm (GA). The results show that our method can reduce the average number of generations by limitation the search space.
Keywords
- Sequential circuit
- combinational circuit
- genetic algorithm
- evolvable hardware
- evolutionary algorithm
How to Cite
P. Soleimani, S. Mirzakuchaki, R. Sabbaghi-Nadooshan, and M. Bagheri, "Improvement of Optimization in Design of Synchronous Sequential Circuits by Using Evolvable Hardware," International Journal of Computer Theory and Engineering, vol. 4, no. 5, pp. 812-815, 2012. https://doi.org/10.7763/IJCTE.2012.V4.584
Copyright & License
Copyright © 2012 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).