Abstract—In this paper, in order to best meet real-time applications of 2-dimensional discrete wavelet transform (2-DDWT) with demanding requirements in terms of speed and throughput, 2-parallel and 4-parallel pipelined lifting-based VLSI architectures for lossless 5/3 and lossy 9/7 algorithms are proposed. The two proposed parallel architectures achieve speedup factors of 2 and 4 as compared with single pipelined architecture based on the first scan method proposed by Ibrahim et al. The advantage of the proposed parallel architectures is that the total temporary line buffer (TLB) doesnot increase from that of the single pipelined architecture proposed by Ibrahim et al. when degree of parallelism is increased.
Index Terms—VLSI architecture, parallel, discrete wavelets transform (DWT), JPEG2000, and lifting scheme
Ibrahim Saeed Koko and Herman Agustiawan are with the Electrical and Electronic Engineering Department, Universiti Teknologi PETRONAS, Perak, Tronoh, Malaysia.
Cite: Ibrahim Saeed Koko and Herman Agustiawan, "Parallel form of the Pipelined Lifting-based VLSI Architectures for Two-dimensional Discrete Wavelet Transform ," International Journal of Computer Theory and
Engineering vol. 1, no. 1, pp. 85-96, 2009.
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